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MC14553B 3-Digit BCD Counter
The MC14553B 3-digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on-chip oscillator provides the low-frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications.
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MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 MC14553BCP AWLYYWW 1
* * * * * * *
TTL Compatible Outputs On-Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset
16 SOIC-16 DW SUFFIX CASE 751G 1 14553B
AWLYYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 +20 500 - 55 to +125 - 65 to +150 260 Unit V V mA A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
mA Device mW C C C MC14553BCP MC14553BDW Package PDIP-16 SOIC-16 Shipping 25/Rail 47/Rail
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14553B/D
MC14553B
BLOCK DIAGRAM
4 CIA 12 10 11 13 CLOCK LE DIS MR 3 CIB Q0 Q1 Q2 Q3 O.F. DS1 DS2 DS3 VDD = PIN 16 VSS = PIN 8
9 7 6 5 14 2 1 15
TRUTH TABLE
Inputs Master Reset 0 0 0 0 0 0 0 0 1 X = Don't Care Clock Disable 0 0 1 LE 0 0 X 0 0 X 1 0 Outputs No Change Advance No Change Advance No Change No Change Latched Latched Q0 = Q1 = Q2 = Q3 = 0
X 1 1 0 X X X
X X X X
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MC14553B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source -- Pin 3 Source -- Other Outputs Sink -- Pin 3 Sink -- Other Outputs Iin Cin IDD IOL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 0.25 - 0.62 - 1.8 - 0.64 - 1.6 - 4.2 0.5 1.1 1.8 3.0 6.0 18 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 0.2 - 0.5 - 1.5 - 0.51 - 1.3 - 3.4 0.4 0.9 1.5 2.5 5.0 15 -- -- -- -- -- - 0.36 - 0.9 - 3.5 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 4.0 8.0 20 0.00001 5.0 0.010 0.020 0.030 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 0.14 0.35 1.1 - 0.36 - 0.9 - 2.4 0.28 0.65 1.20 1.6 3.5 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (3.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) MR = VDD Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc mAdc mAdc Adc pF Adc IT IT = (0.35 A/kHz) f + IDD IT = (0.85 A/kHz) f + IDD IT = (1.50 A/kHz) f + IDD Adc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004.
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MC14553B
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SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic Figure 2a Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Clock to BCD Out Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- 600 400 200 - 80 - 10 0 550 200 150 1200 600 450 - 80 0 20 -- -- -- Typ (7.) 100 50 40 900 500 200 600 400 200 900 500 300 300 200 100 - 200 - 70 - 50 275 100 75 600 300 225 - 180 - 50 - 30 1.5 5.0 7.0 No Limit -- -- -- 1.5/C1 4.2/C1 7.0/C1 15 5.0 4.0 -- -- -- Max 200 100 80 Unit ns 2a tPLH, tPHL tPHL 1800 1000 400 1200 800 400 1800 1000 600 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 2.5 3.5 ns Clock to Overflow 2a ns Reset to BCD Out 2b tPHL ns Clock to Latch Enable Setup Time Master Reset to Latch Enable Setup Time Removal Time Latch Enable to Clock Clock Pulse Width 2b tsu ns 2b trem ns 2a tWH(cl) ns Reset Pulse Width 2b tWH(R) ns Reset Removal Time -- trem ns Input Clock Frequency 2a fcl MHz Input Clock Rise Time 2b tTLH ns Disable, MR, Latch Enable Rise and Fall Times Scan Oscillator Frequency (C1 measured in F) -- tTLH, tTHL fosc s 1 Hz 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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MC14553B
899 900 901 990 991 992 993 994 995 996 997 998 999 1000 UP AT 980 UP AT 800 1000 999 tWL(cl) 50% tPHL 50% tTHL 1/fcl tPHL 50% trem 50% tPHL, tPLH BCD OUT 50% tPHL MASTER RESET 50% tsu tWH(R) 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 UP AT 80 20 ns CL CL CL CL CL 90% CLOCK 10% tPLH BCD OUT OVERFLOW 10% tTLH 20 ns tTLH (b) GENERATOR 1 GENERATOR 2 GENERATOR 3 VDD C LE MR DIS Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 VSS CL CL CL CL CL LATCH ENABLE CLOCK 50% tsu 90% 10% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 UNITS CLOCK UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 TENS CLOCK TENS Q0 TENS Q3 HUNDREDS CLOCK HUNDREDS Q0 HUNDREDS Q3 DISABLE OVERFLOW MASTER RESET SCAN OSCILLATOR DIGIT SELECT 1 DIGIT SELECT 2 DIGIT SELECT 3 UNITS TENS HUNDREDS (DISABLES CLOCK WHEN HIGH) (a) PULSE GENERATOR 16 C LE DIS MR 8 VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 VSS
Figure 1. 3-Digit Counter Timing Diagram (Reference Figure 3)
90%
Figure 2. Switching Time Test Circuits and Waveforms
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MC14553B
OPERATING CHARACTERISTICS The MC14553B three-digit counter, shown in Figure 3, consists of three negative edge-triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs (active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on-chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow output, which provides one pulse for every 1000 counts.
LATCH ENABLE 10 CLOCK 12
The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to digit one; but all three digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. The Disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. Information can be recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle.
C1A 4 SCAN R OSCILLATOR 3 C1B R SCANNER
C1
PULSE GENERATOR
PULSE SHAPER
Q0 Q1 Q2 R / 10 Q3 UNITS C
QUAD LATCH 9 Q0
11 DISABLE (ACTIVE HIGH) Q0 C Q1 Q2 R / 10 Q3 TENS
MULTIPLEXER 7 QUAD LATCH Q1 BCD OUTPUTS (ACTIVE HIGH) 6 Q2
Q0 Q1 Q2 R / 10 Q3 HUNDREDS C
QUAD LATCH
5
Q3
13 MR (ACTIVE HIGH)
14 OVERFLOW
2 1 15 DS1 DS2 DS3 (LSD) DIGIT SELECT (MSD) (ACTIVE LOW)
Figure 3. Expanded Block Diagram
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STROBE RESET 10 4 12 CLK MC14553B DIS 11 LE MR 3 14 0.001 F C1A C1B 10 LE CLK MC14553B DIS O.F. Q3 Q2 Q1 Q0 DS3 DS2 DS1 5 6 7 9 15 12 13 MR 13 C1 A C1 B 4 3 14
CLOCK INPUT 11
12
O.F. Q3 Q2 Q1 Q0 DS3 DS2 DS1 5 6 7 9 15 1 2 5 3 2 A B C a 9 10
VDD
MC14553B
Figure 4. Six-Digit Display
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VDD LSD 5 9 a A 3 B b 10 2 11 C c 12 4 D MC14543B d 6 13 Ph e 1 15 f LD 7 14 BI g
7
VDD
b 11 c 12 4 D MC14543B d 6 13 Ph e 1 15 LD f 7 g 14 BI
DISPLAYS ARE LOW CURRENT LEDs (I peak < 10 mA PER SEGMENT)
MSD
MC14553B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC14553B
PACKAGE DIMENSIONS
SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45 _
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
q
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Notes
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Notes
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MC14553B
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC14553B/D

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